Flipping the script on power-hungry AI workloads, Bengaluru’s SandLogic slashes memory overhead by 90% with ExSLerate—an AI co-processor IP enabling high-efficiency AI on low-power devices. Kamalakar Devaki from SandLogic explains everything to EFY’s Yashasvini Razdan.
Q. How did you come up with this radical idea to venture into processor IP design?
A. We started SandLogic in 2018, but the problem statement we are addressing today has been with us for quite some time. Before founding SandLogic, I worked with companies like Tech Mahindra, Mindtree, and Verizon, primarily as an architect. Around 2017, deep learning was gaining traction, and data sciences were being widely adopted, and one common question that stuck with me was: Why does artificial intelligence (AI) require so much hardware to deploy?
The genesis of ExSLerate was set up with our first project at SandLogic for Tech Mahindra, which was developing a dashcam for driver monitoring. They needed AI models to run on these small devices, but existing solutions were not efficient. To address this, we started developing a tool called CORE (Compile Once, Run Everywhere), inspired by Java’s portability. We envisioned a framework where AI models, regardless of their training environment, could be deployed across multiple devices seamlessly.
While working on CORE, in 2019-2020, we participated in the Microprocessor Challenge, proposing AI capabilities for the Shakti processor. Although we did not make it to the top 10 in the finals, we successfully demonstrated that Shakti could run AI models in the semifinals.
Q. How did you end up receiving the Chips2Startup grant?
A. Around this time, the Indian government launched the C2S (Chips to Startup) programme. We applied, proposing a fully flexible and novel co-processor architecture. Our idea was selected, and we became one of the 13 companies awarded grants for development. Today, we are researching AI models at a fundamental level and analysing the impact of using specific operators on hardware efficiency. This approach allows us to optimise both model design and hardware architecture simultaneously.
Q. When it comes to market positioning, what industries or applications are your primary targets for ExSLerate?
A. We are focusing on consumer devices, medical devices, Internet of Things (IoT) and drone manufacturing—essentially, any device requiring a small form factor and low power consumption. ExSLerate is a general-purpose accelerator, but it supports customisation for specific industries.
Q. What kind of partnerships do you have with semiconductor fabs, cloud AI providers, or embedded system integrators?
A. It is still early in our journey, as we are planning to enter the market by June 2026. However, we have already established partnerships with IMEC and are in discussions with Synopsys for certain intellectual properties (IPs). As part of the C2S programme, we are also engaged with the Design Linked Incentive (DLI) scheme, which provides us access to various tools from Synopsys and other fabrication-related resources. Additionally, we are part of the ChipIN programme. Right now, we are leveraging this ecosystem to take our designs to production. By next January, we will be in a better position to discuss partnerships in greater detail. Currently, our partnership with IMEC provides us access to Taiwan Semiconductor Manufacturing Company (TSMC). We are also engaged with Sasken Technologies, exploring how we can integrate their IPs into our system-on-chips (SoCs).
Q. Do you plan to sell the IP as is, or do you want to take this for tape-out and sell the chip?
A. Our focus is on selling the design and IPs, not the fabricated chips. Even the customers we are discussing are primarily interested in the design rather than the fabrication. They have their own fabrication facilities to manufacture the chips. However, we must first validate our IP. That is the priority—proving that the design works.
Q. So, is the test chip primarily to validate the design?
A. Yes, we are integrating it into an existing product as part of the C2S programme. This is necessary to demonstrate its functionality in a real-world scenario.
Q. Do you plan to sell that chip as well? Fabrication is expensive compared to designing and selling the IP.
A. As part of this testing, we will manufacture only a limited number of chips. These will primarily be provided to ecosystem partners for testing and proof-of-concept (PoC) validations. This will help attract customers by demonstrating the chip’s capabilities rather than selling it in large quantities.
Q. Any revenues?
A. On the chip side, we have received early interest, but no formal transactions have taken place yet. For the IP, we have not sold anything commercially yet. Right now, we are focused on bringing the design to fabrication, which is scheduled for completion by June next year. Currently, we are generating revenue by working on strategic projects for the Defence Research and Development Organisation (DRDO), where we develop specific IPs for them.
Q. What are the biggest challenges you are facing in scaling up?
A. At this stage, our primary focus is proving our IP. The biggest challenge is securing the right partners for validation, packaging, and testing. We do not have a talent shortage—our team has the necessary expertise. However, we need additional funds to scale up. That is why we are currently in the process of raising Series A funding upwards of $25 million.
Q. How do you plan to utilise this $25 million in Series A funding?
A. It will be a mix. A portion will go into R&D. Some of it will be used for building partnerships and conducting PoCs with device manufacturers. The rest will be allocated to sales and market development.
Q. Do you plan to scale this chip for more powerful AI applications, such as larger AI accelerators?
A. The architecture is designed to be scalable. Since it is AXI-compliant and IRE-compliant, it can be configured in multiple ways, including clustering multiple chips for higher processing power. However, for now, our focus remains on small devices, as that itself is a massive market. While it is technically possible to scale for larger AI applications, we do not have immediate plans for that.
Q. Is there a roadmap for supporting advanced AI features, such as on-chip training or federated learning?
A. What we are building today is an inference class chip. However, we are ensuring support for emerging model architectures. For example, large language models (LLMs) are evolving rapidly. The insights we gain from developing LLMs influence our chip design decisions. That is why we invest in AI research—without it, we would not be able to provide meaningful design inputs to our Design team. Our current design already supports new architectures like LFMs( liquid field models), recurrent kernel-weight vectorisation (RKWV), and TITANs .
Q. What is the underlying architecture of the ExSLerate co-processor?
A. ExSLerate is not a host processor. It is an AI processor that can work with both RISC-V and ARM-based host processors. Our processor IP has been tested with both architectures. For instance, the Shakti processor from IIT Madras is RISC-V based, and we have successfully integrated our first version of the accelerator with it.
Q. What types of neural network models is this chip optimised for?
A. ExSLerate supports all widely used NN architectures like convolutional neural networks (CNNs) and transformers, however, as I mentioned earlier, it supports new architectures like LFMs, RKWV, TITANs ensuring versatility across AI applications.
Q. Does it feature in-memory computing, or have you implemented other memory management optimisations?
A. It incorporates elements of in-memory computing while optimising workload execution. We have significantly reduced memory transactions, minimising the need to interact with the host processor for every small operation. For example, traditional AI co-processors like NVIDIA graphics processing units (GPUs) act as external accelerators, frequently communicating with the host processor, leading to high memory transaction overhead. With ExSLerate, we have reduced 90 per cent of the non-essential memory transactions and significantly improved the efficiency of handling tensors. On top of it ExSLerate supports true dynamic sparsity. These features enhance overall efficiency, which is the core objective of our innovation. We have filed a patent for the same.
Q. Is this chip designed with a heterogeneous computing approach?
A. Yes, you are right. It is compatible with AIX and IREE engines. This allows it to integrate into a complex SoC alongside a host processor, neural processing unit (NPU), or GPU. It can coordinate efficiently within these setups.
Q. How does this IP compare to its competitors in terms of power and efficiency? What are the peak and sustained trillion operations per second (TOPS) metrics for this IP?
A. We support dynamic sparsity, support all popular NNs like CNNs, transformers, and also, we support quantisation down to INT4. These features significantly enhance performance compared to competitors. For example, other chips in this space, such as Google’s Edge TPU and Xilinx B10-1024, typically consume five watts of power and give up to four TOPS. Our chip, however, operates at just two watts while delivering 15 trillion operations per second.
The peak performance is 20 TOPS, while sustained performance is around 15 TOPS. If we remove additional engines such as image processing, the minimum performance remains between three and five TOPS.
Q. How does it handle inference in low-power applications during real-time processing?
A. This chip is designed for small devices and real-time inference. We provide a complete supporting infrastructure called EdgeMatrix.io, which allows models to be deployed directly onto the device, eliminating the need for cloud-based inference. The runtime loads the AI model and injects the AI workflow directly into the chip, ensuring the models run efficiently on-device.
Q. What are the latency figures for common AI workloads, such as image recognition, speech processing, or natural language processing (NLP)?
A. The chip supports up to 160 frames per second for image recognition using models like ResNet 50.
Q. What software stack and frameworks does ExSLerate support?
A. It supports all major AI frameworks, including PyTorch, TensorFlow, and Caffe. At the top level, EdgeMatrix.io manages runtime compatibility. It includes built-in compiler and parser support, allowing developers to deploy models directly. It provides a command-line tool that ports models directly onto the chip. We also have APIs for custom kernel development or low-level optimisations integrated into the system.
Q. Will you open source any part of the ExSLerate architecture or software stack?
A. Yes, we plan to open-source the base version. But first, we need to prove its effectiveness through successful integrations. Once that happens, we will definitely open source some parts.
Q. What are your timelines moving forward?
A. By the end of 2026, we aim to open source certain components. Our design will be ready for commercialisation by June 2026. We expect to complete the Series A funding round by June 2025.
Q. What are your current marketing and communication goals, and who is your target audience?
A. We are focused on building early visibility and credibility for ExSLerate and our Edge AI solutions. As I mentioned earlier, our target audience includes device manufacturers in consumer electronics, healthcare, IoT, drones, and embedded system integrators. We are highlighting ExSLerate’s performance, efficiency, and scalable architecture to position SandLogic as a trusted innovator in Edge AI and the semiconductor industry.
Q. What was your goal behind exhibiting at India Electronics Week (IEW)? Was it achieved?
A. Our goal behind exhibiting at IEW was to showcase SandLogic’s Edge AI capabilities — including our on-device small language models, EdgeMatrix runtime stack, and voice and speech technologies — to potential partners, customers, and industry stakeholders. We intended to create early visibility, demonstrate the practical readiness of our technologies, and initiate conversations with device manufacturers and system integrators.
