Through a prolonged partnership, Cadence and TSMC are enhancing AI and HPC chip design, delivering advanced IP, AI-driven tools, and 3D-IC solutions for faster, more efficient semiconductors.
Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) have expanded their collaboration to enhance chip design automation and intellectual property (IP), targeting faster time-to-market for AI and high-performance computing (HPC) applications.
The partnership covers advanced process nodes, including TSMC N3, N2, and A16™, and spans AI-driven electronic design automation (EDA), 3D-ICs, IP, and photonics. Cadence tools such as Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Solution, Pegasus™ Verification System, and Virtuoso® Studio have now been optimised for these technologies.
Furthermore, AI-enabled design flows are available for TSMC’s 3DFabric packaging, and Cadence is developing EDA flows for TSMC’s A14 process, with the first PDK expected later this year. Several new Cadence IP blocks are silicon-proven and available for TSMC N3P.
Moreover, the collaboration includes AI-driven solutions that optimise power, performance, and area (PPA) for TSMC N2 designs. Cadence tools such as JedAI, Cerebrus® Intelligent Chip Explorer, and Innovus+ AI Assistant automate implementation tasks, including design rule check (DRC) violation corrections.
Chin-Chi Teng, senior vice president and general manager of Cadence’s Digital and Signoff Group, said the companies aim to improve design efficiency and support customers developing AI and HPC systems.
Aveek Sarkar, director of Ecosystem and Alliance Management at TSMC, said the partnership helps address challenges in semiconductor development and supports higher performance and energy efficiency in AI systems, while enabling customers to move from design to silicon more quickly.
“Our enduring partnership continues to empower our mutual customers to accelerate their journey to silicon while driving the rapid proliferation of AI,” he said.
For 3D-IC designs, Cadence provides support for TSMC 3DFabric packaging, including bump connections, multi-chiplet alignment, and system-level SI/PI analysis using Clarity™ 3D Solver and Sigrity™ X Platform. Thermal and photonic simulations are enabled through Virtuoso Studio with the Celsius™ Thermal Solver.
Cadence IP for TSMC N3P includes HBM4 memory, LPDDR6/5X, DDR5 MRDIMM Gen2, PCIe® 7.0, eUSB2V2, and UCIe™ 32G, offering options to support high-performance and energy-efficient AI infrastructure.
