Cadence’s Palladium Z3 and a new DPA App profile dynamic power across billion-gate AI designs in a few hours, built on NVIDIA hardware.
Cadence collaborates with NVIDIA in developing a hardware-accelerated power analysis workflow of pre-silicon design, that can analyse billion-gate AI designs across billions of cycles within a few hours, with up to 97 per cent accuracy. The capability runs on the Cadence Palladium Z3 Enterprise Emulation Platform using the Cadence Dynamic Power Analysis (DPA) application.
This collaboration is to address the hardware limits in conventional pre-silicon power analysis. The tools cannot scale beyond a few hundred thousand cycles without impractical timelines. Cadence approach uses hardware acceleration and parallel processing to reduce run time.
The Palladium Z3 Platform uses the DPA App to accurately estimate power consumption under real-world workloads, allowing functionality, power usage and performance to be verified before tapeout, when the design can still be optimized.
Useful in AI, ML and GPU-accelerated applications, early power modeling increases energy efficiency while avoiding delays from over- or under-designed semiconductors.
Dhiraj Goswami, corporate vice-president and general manager at Cadence, said: “This project redefined boundaries, processing billions of cycles in as few as two to three hours.”
“As the era of agentic AI and next-generation AI infrastructure rapidly evolves, engineers need sophisticated tools to design more energy-efficient solutions,” said Narendra Konda, vice president, Hardware Engineering at NVIDIA. “By combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership, we’re advancing hardware-accelerated power profiling to enable more precise efficiency in accelerated computing platforms.”
