Amid India’s semiconductor reset, DLI 2.0 prepares to open doors to Indian-led global consortia, aiming to bridge design-to-deployment gaps and accelerate chip commercialisation.
India is preparing to relaunch its semiconductor design-linked incentive (DLI) scheme under a revised framework, following limited success in the first phase. According to a report by the Financial Express, officials confirmed that the new version, known as DLI 2.0, will allow Indian firms to form consortia with global partners, while ensuring majority domestic ownership. Indian companies will be required to hold at least 51% of equity, with foreign participation capped at 49%.
The move marks a departure from the earlier scheme, which was restricted to startups and small enterprises. Larger Indian firms will now be eligible, reflecting the government’s intention to strengthen commercialisation prospects and attract global expertise.
Meanwhile, the first phase of the DLI programme saw weak traction, with only 24 of around 60 applicants approved and just a handful securing fabrication orders. None of the beneficiaries has yet claimed deployment-linked incentives, as designs have not reached commercialisation.
Officials attributed the limited impact to structural challenges in the startup ecosystem, including difficulties in securing approvals, raising venture funding, and scaling capital-intensive prototype development.
The revised scheme is expected to bridge this gap by involving established firms and international collaboration, while retaining intellectual property within India.
The Ministry of Electronics and IT (MeitY) is also reviewing the incentive structure. Under DLI 1.0, firms could claim reimbursement of up to 50% of design costs, capped at ₹150 million, and deployment incentives of 4–6% of net sales, capped at ₹300 million.
Industry feedback has suggested these limits were inadequate for a sector with high capital requirements and long gestation periods. Adjustments to these ceilings are under consideration.
The revamped scheme, expected to be rolled out by May-June, is intended to accelerate India’s semiconductor design ecosystem and support the creation of commercially viable firms capable of contributing to the global value chain.
