Powered by ChipIN Centre’s expanding ecosystem, India’s chip mission gains traction as SCL Mohali delivers 28 student-built chips, marking a milestone in the nationwide design effort.
The Union Minister for Electronics and Information Technology, Ashwini Vaishnaw, has handed over 28 student-designed chips fabricated at the Semiconductor Laboratory (SCL) in Mohali.
The handover took place on Friday during his visit to review the lab’s progress and modernisation efforts. The batch included 600 bare dies and 600 packaged chips created by students from 17 academic institutions under the Chips to Startup (C2S) programme.
Addressing the audience there, Vaishnaw said India is now emerging as a distinct force in the global semiconductor ecosystem. He noted that universities across the country are using advanced design technologies, helping build a large semiconductor development framework that is ‘unique to India’.
Officials at SCL provided the Minister with a detailed overview of the design-to-fabrication workflow adopted for the student projects.
According to an update by the Ministry of Electronics and Information Technology (MeitY), a major part of this ecosystem is the ChipIN Centre at C-DAC Bengaluru. The facility hosts advanced electronic design automation tools and offers access to compute infrastructure, IP cores, and expert mentorship.
These resources support academic institutions working under the C2S programme and enable students to take their designs through fabrication at SCL.
The ChipIN Centre collects student designs every quarter. After rigorous compliance checks and iterative feedback, the approved designs are merged onto a single mask using a Multi-Project Wafer process.
This approach lowers cost and speeds up fabrication. SCL then manufactures, packages and returns the finished chips to the students.
Over the last year, five MPW shuttle runs were completed. A total of 122 designs from 46 institutions were submitted. SCL fabricated 56 chips across these runs. The batches were taped out in December 2024, February 2025, May 2025, August 2025 and November 2025.
Meanwhile, the scale of participation continues to grow. More than 100,000 students used over 12.5 million hours of design tools during their coursework and research. Startups supported by the programme logged an additional 5 million tool hours, bringing total usage to 17.5 million hours.
Officials said this makes ChipIN one of the world’s largest centralised chip design facilities. Vaishnaw further commented that the progress reflects the government’s long-term goal of building strategic semiconductor self-reliance.
