Under the collaboration, Siemens’ EDA solutions will support critical stages of chip development
Siemens Digital Industries Software and Samsung Foundry strengthen collaboration for semiconductor design and manufacturing capabilities, with a focus on supporting the global fabless ecosystem and accelerating the development of next-generation chips.
The enhanced partnership aims to align Siemens’ electronic design automation (EDA) portfolio with Samsung Foundry’s advanced process technologies, enabling customers to manage increasing design complexity, improve verification accuracy and shorten product development cycles.
Under the collaboration, Siemens’ EDA solutions will support critical stages of chip development, including design, simulation, verification and manufacturing enablement. The companies said the integrated workflows are intended to improve design efficiency and increase the likelihood of first-pass silicon success.
“Samsung Foundry continues to work closely with Siemens to support customers with robust, manufacturing-ready design flows across advanced process technologies,” said Hyung-Ock Kim, Vice President and Head of the Foundry Design Technology Team at Samsung Electronics. He added that the collaboration within Samsung’s SAFE ecosystem is helping customers address growing design challenges and accelerate innovation from design through manufacturing.
A key area of the expanded partnership is the advancement of photonic integrated circuit (PIC) design. Leveraging Siemens’ Calibre software, the joint solution offers capabilities such as equation-based design rule checking, verification of curvilinear layouts and pattern matching, helping improve the manufacturability of increasingly sophisticated photonic devices.
Siemens’ Calibre nmPlatform suite has also been fully qualified for Samsung Foundry’s manufacturing processes, providing support for design rule checking, layout-versus-schematic verification and parasitic extraction.
The companies are also addressing power integrity challenges through automation. Samsung Foundry plans to deploy Siemens’ Calibre DesignEnhancer Pge technology for its 2nm process node, enabling automated power-grid optimisation and mitigation of issues such as electromigration and voltage drop during chip layout.
In the area of design-for-test (DFT), Samsung Foundry is utilising Siemens’ Tessent solutions to enhance yield analysis at advanced nodes. The collaboration includes developing a high-resolution chain-diagnosis flow to improve fault detection and silicon-level failure analysis.
The collaboration also extends to advanced packaging technologies. Samsung Foundry is adopting Siemens’ Innovator3D tools for its 2.3D Cube-E platform, supporting early-stage floorplanning, automated layout generation and verification of complex 2.5D and 3D integrated circuit designs.
Through this partnership, both companies are committed to delivering production-ready semiconductor design solutions and supporting the growing demand for advanced chips across high-performance computing, AI and data-intensive applications.
