TSMC plans to launch its first CoPoS chips by 2026. Full commercial-scale production is targeted for 2029.
Taiwan Semiconductor Manufacturing Company (TSMC) is advancing towards large-scale production of its next-generation packaging CoPoS by 2029, with Nvidia expected to be its first major customer.
The Chip-on-Panel-on-Substrate (CoPoS) platform is an evolution of the company’s established Chip-on-Wafer-on-Substrate (CoWoS) technology, which is widely used for high-performance applications in artificial intelligence. CoPoS is designed to build on two of TSMC’s packaging systems: CoWoS-R, typically used for Broadcom products, and CoWoS-L, developed for clients like Nvidia and AMD.
Unlike traditional CoWoS which relies on circular wafers, CoPoS uses rectangular panels measuring 310x310mm. This approach provides more usable substrate area, allowing for higher output and lower cost per unit. The format is also expected to boost yield rates and power packaging density, critical for increasingly complex AI workloads.
TSMC plans to launch its first CoPoS pilot line by 2026. Full commercial-scale production is targeted for 2029.
The Advanced Packaging 7 campus (AP7) is being built in eight phases, with phase four earmarked for CoPoS. Earlier phases will focus on other advanced packaging formats. Phase one will support Apple’s multi-chip module production, while phases two and three are aligned with SoIC ramp-up plans.
CoWoS manufacturing, meanwhile, is staying at TSMC’s AP8 location, a former Innolux facility, and will not be transferred to the new AP7 site.
The move signals TSMC’s continued focus on advanced packaging leadership as chipmakers demand more powerful solutions for AI, data centres, and high-end computing.
