GF-qualified rule decks are now available to help customers who are designing and taping out hyperscale, aerospace 5G communications, consumer and automotive applications ramp up quickly
Cadence Design Systems, Inc has announced that its Cadence Pegasus Verification System is now qualified for the GlobalFoundries (GF) 12LP/12LP+ and 22FDX technologies.
The collaboration with GF confirmed that the Pegasus Verification System meets the rigorous accuracy and runtime targets customers have come to expect with physical verification for these advanced GF nodes, said the company in a release.
GF-qualified rule decks are now available to help customers who are designing and taping out hyperscale, aerospace 5G communications, consumer and automotive applications ramp up quickly.
“Our collaboration with Cadence helps ensure that customers can use the qualified Pegasus Verification System to create high-quality designs in high-growth markets using our 12LP/12LP+ and 22FDX platforms,” said Richard Trihy, vice president of customer design enablement at GF. “Through the availability of the collateral, we’re also giving customers a fast path to adoption so they can quickly start reaping the benefits of our technologies.”
“Cadence and GF worked together on the Pegasus Verification System qualification to provide customers with added confidence that they can achieve DRC, LVS, metal fill and mandatory DFM requirements on GF’s advanced technologies and get to market faster,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence.
“The Pegasus Verification System provides customers with a compelling offering, given its massive scalability and tight integration with Innovus Implementation and the Virtuoso platform, providing faster physical verification cycles and shorter iterations, which enables them to stay in front of the competition.”
The Pegasus Verification System is part of the broader Cadence digital full flow, which provides optimal power, performance and area (PPA) with a faster path to design closure and supports Cadence’s Intelligent System Design™ strategy, enabling SoC design excellence.
