Avery Design Systems recently announced the release of its fully tested Verification IP (VIP) for 800 Gbps Ethernet, which can now be utilised to perform virtual network co-simulation for a full layer Ethernet 2-7 network stack. The combination of the virtual co-simulation/co-emulation system and a verification IP helps enable the operation of full hardware/software system verification on pre-silicon SoC RTL and software integrations. This further enables the system designers to be able to perform system-level validation of an SoC design’s Ethernet and TCP/IP network interfaces via real network traffic workloads of communication, datacentre, and storage network protocols running on either host OS or virtual machine technology with a company claimed speed of 800 Gbps.
“Leveraging the bandwidth and performance of Ethernet has become increasingly important in a range of data transfer intensive applications and time-to-market is a major concern for product developers. Performing full hardware/software, system-level verification of DPUs, SmartNICs, switches, and routers can be accelerated by weeks to months using virtual network co-simulation. With this solution, any host OS or guest OS (VM) user space program or Linux network utility can communicate with SoC RTL/FW via Avery’s SystemVerilog MAC/PHY virtual NIC VIP,” said Chris Browy, vice president of sales and marketing at Avery.
One of the important applications for utilising Ethernet VIP is NVMe-over-TCP which is applied to TCP application interfaces in pure software-exclusive host driver or optimised hardware offload to implement disaggregated, composable block storage systems for a standard IP and Ethernet network. Additionally, in large, distributed compute server architectures, designers can incorporate NVMe-MI in-band usage models over IP control path networks for centralised discovery and control systems.
The device can be considered as a simple Ethernet device, which rather than receiving packs from a physical media (Ethernet NIC), receives them from the Ethernet MAC/PHY RX VIP which hands them over to the OS network stack. The Ethernet MAC/PHY VIP platform is further connected to the SoC design’s interfaces that are both parts of the SystemVerilog simulation testbench.
