A new cryptographic compute-in-memory architecture has cleared its first validation milestone, targeting faster post-quantum security for connected electronics, automotive, industrial, and IoT systems.
A quantum compute-in-memory (QCIM) architecture has completed its first technical validation milestone, demonstrating hardware acceleration for multiple post-quantum cryptography (PQC) standards. The work, carried out by BTQ Technologies with Taiwan’s Industrial Technology Research Institute (ITRI), advances a chip roadmap led by BTQ and ICTK for integrating quantum-resistant security into electronic systems.
The QCIM core was validated in a TSMC 28-nm design environment and demonstrated cryptographic operations associated with NIST’s FIPS 203, FIPS 204, and FIPS 205 standards. These standards cover ML-KEM, ML-DSA, and SLH-DSA, respectively, providing mechanisms for key establishment and digital signatures designed to withstand attacks from future quantum computers. The validation also demonstrated functional correctness and crypto-agility across multiple PQC algorithms.
The key electronics innovation is the use of compute-in-memory (CIM) for cryptographic processing. Instead of repeatedly moving data between a conventional processor and memory, the architecture performs cryptographic operations within the memory subsystem. This approach is intended to reduce data movement, latency, and power consumption while providing a compact hardware accelerator for security workloads. BTQ describes QCIM as a soft-IP architecture combining symmetric and asymmetric encryption engines for classical as well as post-quantum cryptography.
The architecture is also designed for crypto-agility, allowing security implementations to accommodate evolving algorithms and standards without requiring an entirely new security architecture. This can be important for embedded electronics, where hardware lifecycles can extend for years and replacing deployed security hardware can be costly.
The technology is being positioned for secure MCUs, ASICs, secure elements, edge devices, connected vehicles, industrial equipment, IoT nodes, and Physical AI systems. These applications increasingly require device authentication, secure communications, and long-term protection against emerging cryptographic threats.
The next development stage moves from core validation toward module-level integration, verification, and validation. The work will examine how the QCIM block can be incorporated into larger semiconductor architectures while maintaining interoperability and performance. The roadmap therefore moves the technology closer to system-level evaluation and eventual semiconductor implementation.
