Chandrasekhar announced the DIR-V Program with Prof. V. Kamakoti, Director, IIT Madras as Chief Architect and Shri S. Krishnakumar Rao as Program Manager
The Ministry of Electronics and IT (MeitY) has announced today Digital India RISC-V Microprocessor (DIR-V) Program with an overall aim to enable creation of Microprocessors for the future in India, for the world and achieve industry-grade silicon & Design wins by December’2023.
In an official statement, Minister of State Rajeev Chandrasekhar mentioned that DIR-V will see partnerships between Startups, Academia & Multinationals, to make India not only a RISC-V Talent Hub for the world but also supplier of RISC-V SoC (System on Chips) for Servers, Mobile devices, Automotive, IoT & Microcontrollers across the globe.
Chandrasekhar announced the DIR-V Program with Prof. V. Kamakoti, Director, IIT Madras as Chief Architect and Shri S. Krishnakumar Rao as Program Manager.
He also unveiled the Blueprint of the roadmap of design & implementation of the DIR-V Program with – SHAKTI Processor by IIT Madras and VEGA Processor by C-DAC along with the strategic roadmap for India’s Semiconductor Design & Innovation to catalyze the semiconductor ecosystem in the country.
RISC-V ISA, being available in Open-Source, Dr. Rajendra Kumar, Additional Secretary and Shri Arvind Kumar, Group Coordinator (R&D in Electronics), MeitY projected its growth potential and mentioned that RISC-V will pave the way for next decade of computing design and innovations and adoption in future-generation of processors.
Bob Brennan, VP, Intel Foundry Services, while speaking about the IFS (Intel Foundry Services) Innovation Fund announced by Intel to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem, appreciated the Indian RISC-V movement.
Prof. V. Kamakoti, while highlighting the Intel’s support for getting fabricated 22nm SHAKTI Chip at Intel foundry, mentioned that DIR-V Program will catalyze the design innovation in the country and will encourage the several domestic startups working in RISC-V domains like- micro architecture design, verification and security aspects.
