Strategic collaboration integrates verified intelligence platforms to cut design iteration cycles for AI, automotive, and robotics hardware.
MIPS, a subsidiary of GlobalFoundries, has announced a non-exclusive strategic partnership with Xcelsa Labs to make custom chip design more accessible via Xcelsa’s verified compute intelligence platform. The agreement integrates Xcelsa’s optimisation stack into the MIPS technology ecosystem, helping semiconductor customers streamline design, verification, implementation, and performance tuning for application-specific silicon.
Sameer Wasson, Chief Executive Officer at MIPS, said: “Customers need custom silicon that reflects the real requirements of their software and workloads, delivered within product schedules they can manage.”
He added that combining MIPS’ software-first platform with Xcelsa’s verified intelligence shortens design iterations, preserves functional behavior, and advances workload-native platforms for Physical AI.
Under the partnership, MIPS will deploy Xcelsa’s Apex Design Optimisation platform, which combines physical and verified intelligence to explore design alternatives at AI speeds. The platform’s verified intelligence stack ensures functional equivalence without relying on traditional electronic design automation (EDA) tools, enabling engineers to optimise power, performance, and area (PPA) while drastically reducing cycle times. In production testing, Xcelsa’s platform autonomously closed a timing-violating path in a MIPS load-store unit in under three hours—reducing critical-path delay by 33 per cent compared with a manual workflow that typically takes a month.
Srikanth Jagabathula, Chief Executive Officer and Co-Founder at Xcelsa Labs, noted: “As AI workloads become more specialised, the industry needs a faster way to move from workload requirements to high-performance, production-ready hardware.”
Dylan Patel, Founder and Chief Executive Officer at SemiAnalysis, emphasised: “Efficiency gains now come from silicon built for the specific workload. The problem is that software iterates in weeks and hardware design cycles run in years.”
