Ramesh has built Domain-Specific Accelerators targeting Many-Core, GPU, ASIC, and FPGA Platforms.
The Silicon Integration Initiative (Si2) has recently appointed Ramesh Narayanaswamy, an R&D Scientist at Synopsys, as the new Vice Chair of the Si2 Large Language Model Benchmarking Coalition (LBC).
He works on Synopsys’ Verification and Design Products, specialising in Simulation Performance/Acceleration and ML/AI/GenAI Applications in EDA. He takes care the development of GenAI RTL Design and Verification Agents.
Ramesh has built Domain-Specific Accelerators targeting Many-Core, GPU, ASIC, and FPGA Platforms. Over a 30+ year career, Ramesh has architected and led development of Simulation Software, Simulation Acceleration ASICs & Compilers, and FPGA-based Emulators.
The tools Ramesh built have been used to verify Processor and Peripheral Chips in many generations of GPUs, Mobile devices, and Compute Servers. He has 12 granted patents.
