Launched in 2021 and operationalised in 2022, the India Semiconductor Mission (ISM) is driving India’s ambition to build a self-reliant semiconductor ecosystem spanning manufacturing, design, talent, and supply chains. In this exclusive interview, Dr Satya Gupta, President of the VLSI Society of India (VSI), speaks with Shri Amitesh Kumar Sinha, Additional Secretary, MeitY, and CEO of ISM, about the mission’s progress, challenges, and roadmap for India’s semiconductor future.
Q. You have been associated with the ISM since its inception. Looking back over the past four-and-a-half years, how would you assess its progress, achievements, and key challenges?
A. The Union Cabinet approved the India Semiconductor Policy and the ISM on 15th December 2021, marking India’s first comprehensive semiconductor policy backed by a long-term vision and strong commitment from Prime Minister Shri Narendra Modi and the Union Minister of Electronics and Information Technology, Shri Ashwini Vaishnaw.
Our biggest challenge at the outset was the absence of a semiconductor ecosystem. Without one, attracting global manufacturers is extremely difficult. The first proposals we received were not sufficiently convincing, and because semiconductor manufacturing is highly complex, particularly for a first-time entrant like India, we approved only those projects with a high probability of success.
To ensure this, we established rigorous evaluation criteria and constituted committees of global techno-commercial experts. Every project had to satisfy three non-negotiable requirements:
• Strong financing. Applicants needed deep financial strength backed by profitable or cash-rich parent companies capable of withstanding the cyclical nature of the semiconductor industry. Many early applicants were attracted primarily by government incentives, so identifying genuinely committed partners took time.
• Credible technology transfer. We required complete production-ready technology transfer rather than simple licensing agreements. This included equipment specifications, workforce training, utility planning, installation support, prototype wafer runs, and qualification processes.
• Customer off-take. Technology partners had to commit production and bring established customers, giving global buyers confidence in India’s new manufacturing facilities.
The first company to meet all three criteria was Micron Technology. As an integrated device manufacturer (IDM), it already possessed financing, proprietary technology, and captive demand. Its entry was a turning point, signalling India’s seriousness to the global semiconductor industry.
That breakthrough was followed by strong proposals from Indian companies, including Tata Electronics for wafer fabrication and packaging, and packaging proposals from CG Power and Industrial Solutions and Kaynes Technology.
Our advisory committee, comprising leading members of the Indian diaspora and global semiconductor experts, also helped refine the policy. They recommended simplifying incentives and making them uniform across silicon, display, and compound semiconductor fabs, as well as assembly, testing, marking, and packaging (ATMP) facilities. They also advised that packaging would naturally precede fabrication, helping establish the broader ecosystem. Today, we have approved 12 semiconductor projects under this framework.
Alongside manufacturing, we recognised that semiconductor design is one of India’s greatest strengths. Under the Design-Linked Incentive (DLI) scheme, 24 companies have received financial support, while more than 100 companies have been given access to world-class electronic design automation (EDA) tools following rigorous technical and commercial evaluation. Significantly, 15 of these startups have already secured institutional venture capital funding, with further investment continuing to flow into the ecosystem.
The Tata Electronics semiconductor fab at Dholera, Gujarat, represents another major milestone. Building India’s first wafer fab has been a nationwide learning exercise involving Tata Electronics, Powerchip Semiconductor Manufacturing Corporation (PSMC), the ISM, central and state governments, and construction partners such as Larsen & Toubro (L&T) and Tata Projects. Together, we have gained valuable experience in specialised infrastructure, uninterrupted power and water supply, logistics, customs, international talent, equipment movement, and regulatory requirements, while continuously refining policies to address emerging challenges.
We expect commercial production from the Tata fab to begin by 2028. Furthermore, market demand is already encouraging. Tata has secured strong customer interest across multiple technology nodes, exceeding the capacity of its initial facility. Our packaging programme has progressed even faster. Micron Technology has already started commercial production, Kaynes Technology has commenced manufacturing, and two more ATMP projects are expected to begin production later in 2026. Overall, this has been an excellent start to India’s semiconductor journey.
So, all these developments in the last four-and-a-half years have given us a good base, and it has created confidence in Indian industry, as well as outside India, and as a result of that, now we are seeing a lot of traction from foreign companies from Japan, South Korea, Singapore, Malaysia, Europe, and the US. They are looking at the Indian market strategically and they clearly understand that there is a scope of development here. The semiconductor industry is going to happen here. This kind of confidence building is the greatest satisfaction, and we believe that going forward, we will attract more and more companies.
In a nutshell, the incentive amount announced by the government of India is now fully committed, and we have 12 manufacturing and 24 design projects with us.
Q. When ISM 1.0 was formulated, the 28nm node was widely considered the optimal starting point for India. When do you expect India to have operational 28nm production for domestic chip designers?
A. The more mature nodes above 28nm should enter commercial production by 2028, while 28nm production is expected by 2029.
Q. So, India can realistically expect indigenous commercial production at the 28nm node by around 2029?
A. Yes, absolutely.
Q. New fabs typically face high initial production costs, while global competition demands competitive pricing, high yields, and quick turnaround times. When Tata begins production in 2028-29, do you believe it will be able to match international standards in quality, turnaround time, and cost?
A. Yes, I am confident it will, for two reasons.
First, government incentives cover up to 70% of the capital expenditure, leaving companies to fund only the remaining 30%. This significantly reduces their financial burden and places them on a level playing field with long-established global fabs.
Second, Tata, its engineering team, and its technology partner, PSMC, have the expertise needed to meet global standards. Wafer costs depend primarily on manufacturing yield and operating expenditure (OpEx). I am confident Tata will rapidly achieve yields comparable to those of PSMC. The company is also broadening its technology base through collaborations with global leaders, including Analog Devices Inc. (ADI).
India also enjoys structural cost advantages. Manpower accounts for roughly 13% of a fab’s operating costs and electricity around 17%, both of which are more competitive than in many countries, including China. In addition, key raw materials such as speciality chemicals and industrial gases are already available domestically and can be refined to semiconductor-grade quality, reducing procurement costs by an estimated 5% to 7%.
Production costs may be higher during the first year or two as operations stabilise and yields improve. However, once the production line is fully optimised, there is no structural reason why Tata’s wafer costs cannot be globally competitive.
Q. Packaging has been one of the biggest successes of the ISM. Excluding Micron, what packaging capabilities can we expect from Indian projects by 2027?
A. By the end of 2027, Indian facilities will offer wire-bond, flip-chip, and the first generation of advanced packaging. In 2028, a dedicated 3D glass substrate facility will begin commercial production, significantly expanding our advanced packaging capabilities.
By then, Tata Electronics will also have established its packaging facility and introduced multiple advanced packaging technologies. The company has already signed an MoU with Intel Corporation for technology transfer in advanced packaging.
Together, these developments will provide a comprehensive portfolio ranging from wire-bond and flip-chip to advanced packaging. We are also expanding the ecosystem through projects such as the Intel-3D Glass Solutions initiative, which includes a US$3.3 billion advanced packaging facility under Semicon India 2.0. While 3D Glass Solutions is initially setting up a smaller facility in Bhubaneswar, the larger outsourced semiconductor assembly and test (OSAT) project with Intel will firmly position India on the global advanced packaging map. We are also in discussions with several other global companies, and I believe packaging will become one of India’s greatest strengths.
Q. Many chip design companies require standard ball grid array (BGA) and flip-chip BGA packaging. By 2027, how many approved projects do you expect to offer these commercially?
A. We expect three to four companies to be commercially offering both BGA and flip-chip packaging by then. By 2027, India should have multiple domestic companies offering commercial BGA and flip-chip BGA packaging, with more advanced packaging scaling up from 2028 onwards.
Q. The DLI scheme has created considerable momentum for India’s fabless ecosystem. How do you see it evolving under Semicon India 2.0?
A. The DLI scheme operates through three levels of support.
The first is access to world-class electronic design automation (EDA) tools, not only for startups and micro, small, and medium enterprises (MSMEs) but also for academic institutions, enabling teaching, research, and commercial product development without high upfront costs.
The second is seed funding, which has enabled 24 approved startups to begin designing proprietary chips. Their technologies have attracted institutional venture capital because investors recognise their commercial potential. Collectively, these companies have attracted VC funding exceeding four times the total incentives disbursed under the DLI scheme, demonstrating the scheme’s effectiveness in catalysing private investment and strengthening the domestic semiconductor design ecosystem.
The third is the deployment-linked incentive. Although none of the startups has yet reached this stage, we expect the first commercial chip deployments within the next two to three months. Around a year after successful market deployment, these companies will become eligible for deployment-linked incentives.
Our experience has also highlighted structural gaps that will be addressed under Semicon India 2.0. Even so, the current policy has successfully encouraged 24 hardware startups to enter this highly challenging sector.
The next phase will significantly strengthen India’s fabless ecosystem by extending participation beyond startups and MSMEs to large Indian companies. We are also introducing specialised financial and operational support mechanisms. Although I cannot disclose the details until the policy receives final financial approval, it will provide a comprehensive framework for scaling India’s fabless semiconductor industry.
Q. India currently consumes around US$50 billion worth of semiconductors annually. Given this opportunity, what is a realistic revenue target for India’s fabless sector by 2030?
A. The key challenge for Indian fabless startups is competing with two established groups: western multinational companies and Chinese semiconductor firms.
Displacing Chinese suppliers will depend significantly on government policy. Many Chinese companies benefit from opaque cost structures, while India also has cybersecurity and national security concerns around imported hardware. Accordingly, the government is introducing trusted sourcing regulations. A good example is MeitY’s recent framework for CCTV and public surveillance systems, which encourages electronics manufacturing services (EMS) companies to adopt trusted, locally designed silicon. Such measures will create a stable domestic market for Indian fabless companies.
Against Western competitors, I believe Indian firms can compete effectively on cost because of government support, India’s engineering talent, and lower design costs.
Rather than setting a rigid revenue target, it is important to recognise that startups are inherently unpredictable; many will fail, some will be acquired, and a few will grow into major companies. Nevertheless, based on the overall trajectory, I believe Indian fabless companies can collectively achieve US$2 billion-US$3 billion in revenue by 2030, with the first commercial tape-outs already taking place in 2026, followed by successive waves in 2027 and 2028. As these companies build customer confidence, we expect India to develop a mature fabless ecosystem with 10-15 globally significant design companies.
Q. As a conservative benchmark for the ISM, would it be reasonable to target aggregate revenues of US$100-500 million for Indian fabless companies by 2030?
A. Yes. That is a very reasonable and conservative baseline. I believe the industry will significantly exceed that range. The operational issues affecting this growth have already been discussed extensively within the ISM, and we are prepared to address them structurally under Semicon India 2.0.
Q. Chip design is a major focus of the DLI scheme. The Chips to Startup (C2S) programme has become one of the world’s largest academic semiconductor initiatives. Could you outline the programme’s structure and achievements so far?
A. The C2S programme has been highly successful. We initially set a target of training 85,000 semiconductor engineers and have already upskilled 67,000.
Under Semicon India 2.0, the programme will expand further, with participation expected to reach at least 500 institutions. Beyond providing EDA tools, C2S enables students to take their designs through fabrication and packaging, giving them hands-on experience with physical silicon and preparing them as industry-ready chip designers.
These graduates can establish startups, join Indian semiconductor companies, or work for global MNCs, strengthening the national talent pool. We also expect this expanding ecosystem to generate many more fabless proposals under Semicon India 2.0. In addition, more than 100 commercial organisations have already gained access to EDA tools and are developing chip architectures while awaiting the next phase of the policy.
Q. Although C2S has greatly expanded access to chip design tools, complete system-on-chip (SoC) tape-outs remain limited because multi-project wafer (MPW) runs are expensive, often costing ₹800,000-1 million for just 1mm². As India moves towards 28nm manufacturing, is the government considering support for large-scale academic SoC tape-outs on advanced nodes?
A. We are actively expanding international partnerships to provide subsidised MPW runs. Through the ChipIN Centre, we already coordinate institutional collaborations for funded tape-outs.
This year alone, 240 chips have been taped out: 175 at the Semi-Conductor Laboratory (SCL), Mohali, and 65 through international foundries such as TSMC, GlobalFoundries, and others on advanced node at 28nm and 12nm. At the same time, we must be pragmatic. Most university projects are undertaken by temporary student teams and are intended primarily for learning rather than commercialisation. Therefore, funding academic tape-outs on leading-edge nodes such as 2nm, 3nm, or 12nm is generally not the best use of public resources, unless the design has clear commercial potential.
For engineering education, mature technology nodes are sufficient to build core design skills. However, the ChipIN Centre will continue negotiating access to advanced international foundries. If a university develops an outstanding SoC with genuine commercial or strategic value, the government will provide the necessary financial and fabrication support.
Q. EFY has inspired generations of electronics engineers a₹nd entrepreneurs. What message would you like to give future generations considering careers in semiconductors?
A. I encourage them to seriously consider careers in electronics and semiconductors. This is a multidisciplinary field that requires expertise not only in electronics but also in physics, chemistry, mathematics, metallurgy, and materials science.
India’s semiconductor future is extremely promising. This is becoming a highly rewarding career path, much like computer science. Taiwan’s experience shows that semiconductor engineering salaries eventually matched or exceeded those in software, and I believe India will follow a similar trajectory.
The sector also offers opportunities to work on world-class research and development (R&D) without leaving the country. In the past, many talented Indian students pursued advanced studies abroad because they saw limited opportunities at home. That is changing. India is building an integrated ecosystem spanning chip design, fabrication, packaging, chemicals, gases, industrial infrastructure, and power electronics, allowing engineers to build global careers while contributing to the country’s technological growth.
To support this, the government is introducing specialised curricula and vocational programmes through CBSE, AICTE, the IITs, IISc, and other institutions. The future is extremely bright for anyone who wants to be part of India’s semiconductor journey.
Q. Before we conclude, what gives global investors the confidence to commit to India’s semiconductor ecosystem?
A. The most important point is the government of India’s long-term commitment to the semiconductor sector. Global companies invest only when they have confidence in policy stability.
Our honourable prime minister, Shri Narendra Modi ji, has repeatedly stated at successive Semicon India summits that semiconductor development is a long-term national strategy, with government support extending over the next 20 to 25 years. This policy certainty, reinforced by funding commitments in the Union Budget, has given investors confidence that Semicon India 2.0, 3.0, 4.0 and beyond will continue seamlessly.
That commitment is reflected not only in policy but also in sustained engagement. The Prime Minister and the Minister for Electronics and Information Technology personally participate in Semicon India events and engage directly with global industry leaders, supported by continuous outreach throughout the year.
India also offers one of the world’s most competitive semiconductor incentive frameworks. The implementing agencies operate with transparency, minimise bureaucratic hurdles, and work closely with state governments to ensure projects move forward efficiently. This strong institutional commitment has become one of the key reasons the industry is gaining global confidence.
Q. Finally, if you were to assess the ISM’s journey over the past four-and-a-half years, how would you rate its progress?
A. Despite geopolitical shifts, supply chain disruptions, AI-driven demand, and changing global industry dynamics, the project is progressing extremely well. I would rate the journey eight or nine out of ten.
